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| a Ultralow Power, +3.3 V, RS-232 Notebook PC Serial Port Drivers/Receivers ADM560/ADM561 FUNCTIONAL BLOCK DIAGRAM +3.3V INPUT 12 C1+ +3.3V TO +6.6V VOLTAGE DOUBLER +6.6V TO -6.6V VOLTAGE INVERTER T1 T2 T3 T4 R1 R2 R3 R4 R5 GND 10 VCC 11 V+ 13 V- 17 1F 10V 14 C1- 15 C2+ 16 C2- 1F 6.3V 0.1F FEATURES RS-232 Compatible Operates with 3 V or 5 V Logic Ultralow Power CMOS: 1.3 mA Operation Low Power Shutdown: 0.2 A Suitable for Serial Port Mice 116 kbits/s Data Rate 1 F Charge Pump Capacitors Single +3 V to +3.6 V Power Supply Two Receivers Active in Shutdown (ADM560) APPLICATIONS Laptop Computers Palmtop Computers Notebook Computers Peripherals Modems Printers Battery Operated Equipment GENERAL DESCRIPTION CMOS INPUTS 1F 10V 1F 10V T1OUT T2OUT T3OUT T4OUT R1 IN R2 IN R3 IN R4 IN R5 IN SHDN (ADM561) SHDN (ADM560) EIA/TIA-232 INPUTS EIA/TIA-232 OUTPUTS T1 IN T2 IN T3 IN T4 IN R1 OUT R2 OUT CMOS OUTPUTS R3 OUT R4 OUT R5 OUT EN (ADM560) EN (ADM561) 7 6 20 21 8 5 26 22 19 24 2 3 1 28 9 4 27 23 The ADM560/ADM561 are four driver/five receiver interface devices designed to meet the EIA-232 standard while operating with a single +3.3 V power supply. The devices feature an onboard dc-to-dc converter, eliminating the need for dual 5 V power supplies. This dc-dc converter contains a voltage doubler and voltage inverter which internally generates 6.6 V from the input +3.3 V power supply. The ADM560 and ADM561 consume only 5 mW making them ideally suited for battery and other power-sensitive applications. A shutdown facility is also provided which reduces the power to 0.66 W. The ADM560 contains active low shutdown and active high receiver enable signals. In shutdown mode, two receivers remain active thereby allowing monitoring of peripheral devices. This feature allows the device to be shut down until a peripheral device begins communication. The active receivers can alert the processor which can then take the ADM560 out of the shutdown mode. The ADM561 features active high shutdown and an active low receiver enable. In this device all receivers are disabled in shutdown. The ADM560/ADM561 is fabricated using CMOS technology for minimal power consumption. It features a high level of overvoltage protection and latch-up immunity. The receiver inputs 18 25 ADM560 ADM561 can withstand up to 25 V levels. The transmitter inputs can be driven from either 3 V or 5 V logic levels. This allows operation in mixed 3 V/5 V power supply systems. The ADM560/ADM561 is packaged in a 28-pin SO and a 28-pin SSOP package. ORDERING GUIDE Model ADM560JR ADM560JRS ADM561JR ADM561JRS Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C Package Option R-28 RS-28 R-28 RS-28 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 ADM560/ADM561-SPECIFICATIONS unless otherwise noted.) Parameter Output Voltage Swing Min 5.0 4 VCC Power Supply Current Shutdown Supply Current Input Logic Threshold Low, VINL Input Logic Threshold High, VINH Logic Pullup Current EIA-232 Input Voltage Range EIA-232 Input Threshold Low EIA-232 Input Threshold High EIA-232 Input Hysteresis EIA-232 Input Resistance CMOS Output Voltage Low, VOL CMOS Output Voltage High, VOH CMOS Output Leakage Current Output Enable Time Output Disable Time Receiver Propagation Delay TPHL TPLH Instantaneous Slew Rate Transition Region Slew Rate Typ 5.5 4.5 1.3 2.2 0.2 2 3.0 5 0.4 2.4 3 -25 0.4 0.8 1.1 0.3 5 20 +25 2.4 7 0.4 5 Max Units Volts Volts mA mA A V V A V V V V k V V A ns ns s s V/s V/s mA (VCC = +3.3 V 10%, C1-C4 = 1 F. All specifications TMIN to TMAX Test Conditions/Comments VCC = 3.3 V, Three Transmitter Outputs Loaded with 3 k to Ground VCC = 3.0 V, All Transmitter Outputs Loaded into 3 k to Ground No Load, TIN = VCC No Load,TIN = GND SHDN = GND (ADM560); SHDN = VCC (ADM561), TIN = VCC TIN, EN, EN, SHDN, SHDN, TIN, EN, EN, SHDN, SHDN TIN = GND 3 2.8 0.05 200 300 0.4 1.3 5.0 IOUT = 1.6 mA IOUT = -40 A EN = VCC, EN = GND, 0 V ROUT VCC 1 2 30 Transmitter Output Resistance RS-232 Output Short Circuit Current Specifications subject to change without notice. 300 10 CL = 50 pF, RL = 3 k-7 k RL = 3 k, CL = 2500 pF Measured from +3 V to -3 V or -3 V to +3 V VCC = V+ = V- = 0 V, VOUT = 2 V ABSOLUTE MAXIMUM RATINGS* (TA = +25C unless otherwise noted) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VCC -0.3 V) to +14 V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -14 V Input Voltages TIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (V+, +0.3 V) RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . (V+, +0.3 V) to (V-, -0.3 V) ROUT . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VCC +0.3 V) Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Power Dissipation SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Operating Temperature Range Commercial (J Version) . . . . . . . . . . . . . . . . . .0C to +70C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec). . . . . . . . . . . . . +300C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000 V *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. -2- REV. 0 ADM560/ADM561 PIN FUNCTION DESCRIPTION PIN CONFIGURATIONS Mnemonic VCC V+ V- GND C1+, C1- C2+, C2- TIN Function Power Supply Input 3.3 V 10%. Internally Generated Positive Supply (+6.6 V Nominal). Internally Generated Negative Supply (-6.6 V Nominal). Ground Pin. Must Be Connected to 0 V. External Capacitor 1 Is Connected Between These Pins. External Capacitor 2 Is Connected Between These Pins. Transmitter (Driver) Inputs. These Inputs Accept 3 V or 5 V Logic Levels. An Internal 400 k Pull-Up Resistor to VCC Is Connected On Each Input. Transmitter (Driver) Outputs (Typically 6 V). Receiver Inputs. These inputs accept RS-232 Signal Levels. An Internal 5 k Pull-Down Resistor to GND Is Connected on Each of These Inputs. Receiver Outputs. These are 3 V Logic Levels. Receiver Enable (Active High on ADM560); Active Low on ADM561) Refer to Table I. Shutdown Control (Active Low on ADM560); (Active High on ADM561) Refer to Table I. T3OUT T1OUT T2OUT R2 IN R2 OUT T2IN T1IN R1 OUT R1 IN 1 2 3 4 5 6 7 8 9 28 T4OUT 27 R3 IN 26 R3 OUT SHDN (ADM560) SHDN (ADM561) EN (ADM560) 24 EN (ADM561) 25 ADM560 ADM561 TOP VIEW (Not to Scale) 23 R4 IN 22 R4 OUT 21 20 T4IN T3IN GND 10 VCC 11 19 R5 OUT 18 R5 IN 17 V- C1+ 12 V+ 13 C1- 14 16 C2- 15 C2+ TOUT RIN ROUT EN/EN SHDN/SHDN Table I. ADM560 Normal Operation SHDN = 1 EN = 1 Receivers Active EN = 0 Receivers Inactive SHDN = 0 EN = 1 Receivers R1-R3 Inactive EN = 1 Receivers R4 & R5 Active EN = 0 Receivers R1-R5 Inactive ADM561 SHDN = 0 EN = 0; Receivers Active EN = 1; Receivers Inactive SHDN = 1 EN = 0; Receivers Inactive EN = 1; Receivers Inactive Shutdown Mode REV. 0 -3- ADM560/ADM561 GENERAL DESCRIPTION S1 VCC C1 S2 GND S4 VCC C3 S3 V+ = 2VCC The ADM560/ADM561 are RS-232 transmission line drivers/ receivers which operate from a single +3.3 V supply. This is achieved by integrating step up voltage converters and level shifting transmitters and receivers onto the same chip. CMOS technology is used to keep the power dissipation to an absolute minimum. The ADM560/ADM561 is a modification, enhancement and improvement to the AD230-AD241 family and derivatives thereof. It is essentially plug-in compatible and does not have materially different applications. The ADM560/ADM561 contains an internal voltage doubler and a voltage inverter which generates 6.6 V from the +3.3 V input. Four external 1 F capacitors are required for the internal voltage converter. CIRCUIT DESCRIPTION INTERNAL OSCILLATOR Figure 1. Charge Pump Voltage Doubler S1 V+ FROM VOLTAGE DOUBLER GND C2 S2 S4 V- = - (V+) C4 S3 GND The internal circuitry consists of three main sections. These are: 1. A charge pump voltage converter 2. 3 V Logic to EIA-232 transmitters 3. EIA-232 to 3 V Logic receivers. Charge Pump DC-DC Voltage Converter INTERNAL OSCILLATOR Figure 2. Charge Pump Voltage Inverter The Charge Pump Voltage converter consists of an oscillator and a switching matrix. The converter generates a 6.6 V supply from the input +3.3 V level. This is done in two stages using a switched capacitor technique as illustrated below. First, the 3.3 V input supply is doubled to 6.6 V using capacitor C1 as the charge storage element. The 6.6 V level is then inverted to generate -6.6 V using C2 as the storage element. Capacitors C3 and C4 are used to reduce the output ripple. Their values are not critical and can be reduced if higher levels of ripple are acceptable. The charge pump capacitors C1 and C2 may also be reduced at the expense of higher output impedance on the V+ and V- supplies. The V+ and V- supplies may also be used to power external circuitry if the current requirements are small. Transmitter (Driver) Section Unused inputs may be left unconnected, as an internal 400 k pull-up resistor pulls them high forcing the outputs into a low state. The input pull-up resistors typically source 8 A when grounded so unused inputs should either be connected to VCC or left unconnected in order to minimize power consumption. Receiver Section The receivers are inverting level shifters which accept EIA-232 input levels and translate them into 3 V logic output levels. The inputs have internal 5 k pull-down resistors to ground and are also protected against overvoltages of up to 25 V. The guaranteed switching thresholds are 0.4 V minimum and 2.4 V maximum. Unconnected inputs are pulled to 0 V by the internal 5 k pull-down resistor. This, therefore, results in a Logic 1 output level for unconnected inputs or for inputs connected to GND. The receivers have schmitt trigger input with a hysteresis level of 0.3 V. This ensures error-free reception for both noisy inputs and for inputs with slow transition times. ENABLE AND SHUTDOWN The Drivers convert 3 V or 5 V logic input levels into EIA-232 output levels. With VCC = +3.3 V and driving an EIA-232 load, the output voltage swing is typically 5.5 V. Table I shows the truth table for the enable and shutdown control signals. When disabled, all receivers are placed in a high impedance state. In shutdown, all transmitters are disabled and all receivers on the ADM561 are disabled. On the ADM560, receivers R4 and R5 remain enabled in shutdown. -4- REV. 0 ADM560/ADM561 Typical Performance Curves 6 0 TA = +25C VCC = +3.3V 4 TRANSMITTERS LOADED WITH RL = 5k || CL C1 - C4 = 1F 5 160kbps 80kbps 20kbps -1 4 VOH - Volts -2 VOL - Volts 3 TA = +25C VCC = +3.3V 4 TRANSMITTERS LOADED WITH RL = 5k || CL C1 - C4 = 1F -3 2 -4 160kbps -5 20kbps 80kbps 1 0 0 500 1000 1500 2000 2500 3000 LOAD CAPACITANCE - pF -6 0 500 1000 1500 2000 2500 3000 LOAD CAPACITANCE - pF Figure 3. Transmitter Output Voltage High vs. Load Capacitance Figure 6. Transmitter Output Voltage Low vs. Load Capacitance 6.25 TA = +25C C1 - C4 = 1F VCC = +3.3V TRANSMITTERS UNLOADED 5.75 TOUTHIGH SLEW RATE - V/s 7.5 TA = +25C VCC = +3.3V RL = 5k C1 - C4 = 1F 6.5 | TOUT | - Volts 5.5 4 TRANSMITTERS LOADED 4.5 3 TRANSMITTERS LOADED 5.25 TOUTLOW 3.5 4.75 0 1 2 3 4 5 | IOUT | - mA 2.5 0 500 1000 1500 2000 2500 3000 LOAD CAPACITANCE - pF Figure 4. Transmitter Output Voltage vs. Load Current Figure 7. Transmitter Slew Rate vs. Load Capacitance 10.5 9.5 -3 TA = +25C C1 - C4 = 1F TRANSMITTERS LOADED WITH 5k || 2500pF -4 -5 VOL - Volts 8.5 VOH - Volts 7.5 1 TRANSMITTER LOADED TA = +25C C1 - C4 = 1F TRANSMITTERS LOADED WITH 5k || 2500pF 4 TRANSMITTERS LOADED -6 -7 1 TRANSMITTER LOADED -8 -9 4 TRANSMITTERS LOADED 6.5 5.5 4.5 3.5 2.5 3.0 3.5 4.0 VCC - Volts 4.5 5.0 5.5 -10 2.5 3.0 3.5 4.0 VCC - Volts 4.5 5.0 5.5 Figure 5. Transmitter Output Voltage High vs. VCC Figure 8. Transmitter Output Voltage Low vs. VCC REV. 0 -5- ADM560/ADM561 10 TA = +25C VCC = 3.3V C1 - C4 = 1F ALL TRANSMITTERS UNLOADED OUTLINE DIMENSIONS Dimensions shown in inches and (mm). OUTPUT VOLTAGE V+, V- - Volts 5 28-Lead SO (R-28) C1940-5-7/94 0.037 (0.94) 0.022 (0.559) 0 V+ AND V- EQUALLY LOADED V+ LOADED NO LOAD ON V- V- LOADED NO LOAD ON V+ 28 15 0.299 (7.6) 0.291 (7.39) PIN 1 1 14 0.414 (10.52) 0.398 (10.10) -5 -10 0 5 10 13 15 20 25 0.708 (18.02) 0.696 (17.67) 0.096 (2.44) 0.089 (2.26) 0.03 (0.76) 0.02 (0.51) CURRENT - mA Figure 9. V+, V- vs. Load Current 0.01 (0.254) 0.006 (0.15) 0.05 (1.27) BSC 0.019 (0.49) 0.014 (0.35) 0.013 (0.32) 0.009 (0.23) 6 0 0.042 (1.067) 0.018 (0.457) 1. LEAD NO. IDENTIFIED BY A DOT. 28-Lead SSOP (RS-28) 28 15 0.212 (5.38) 0.205 (5.207) 0.311 (7.9) 0.301 (7.64) PIN 1 1 14 0.407 (10.34) 0.397 (10.08) 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC 0.009 (0.229) 0.005 (0.127) 8 0 1. LEAD NO. 1 IDENTIFIED BY A DOT. 2 LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED -6- REV. 0 PRINTED IN U.S.A. |
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